Performance Analysis of Load Flow Computation Using Fpga

1 The research reported in this paper was supported by the United States Department of Energy (DOE) under Grant No. CH11171. The authors are also grateful to PJM Interconnection for data provided. Abstract – Full-AC load flow constitutes a core computation in power system analysis. Current techniques for solving full-AC load flow rely on the iterative solution of the load flow equations using the Newton-Raphson method, and the bulk of this computation is devoted to solving a sparse-linear system needed for the update each iteration. In this paper, we evaluate the performance gain that is possible with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA). Using benchmark data, from four representative power systems, we compare the performance of a software solution using UMFPACK, a state-of-the-art sparse linear solver, running on a high-end PC with the proposed hardware solution. Performance of the hardware solution is obtained from a parameterized simulation of the hardware that allows a variety of architectural configurations and can take into account different FPGA technology. Our studies show that the proposed hardware solution can provide an order of magnitude performance gain using existing FPGA technology.